Integrated circuits are found in a variety of electronic and computer products. Integrated circuits are interconnected networks of electrical components formed on a common foundation or substrate. Manufacturers typically use techniques such as layering, doping, masking, and etching to build thousands and even millions of microscopic resistors, transistors, and other electrical components on a silicon wafer. These components are then wired, or interconnected, together to form a specific electric circuit, for example, a computer memory.
Typically, the components are covered with an insulating layer of silicon dioxide. Then, small holes, or “vias,” are etched in the insulating layer to expose portions of the components underneath. Trenches are then dug in the layer to define a wiring pattern. Thus, millions of microscopic components are interconnected. Then, through metallization, the holes and trenches are filled to form sub-micron diameter wires between the components.
The semiconductor industry uses a damascene or dual damascene process to form the interconnects. The damascene process involves forming patterns in a dielectric layer (etching), filling the resulting pattern with interconnect metal, then polishing away the excess metal on the wafer surface and leaving inlaid interconnect metal features.
Aluminum has traditionally been used as the conductive interconnect material. In making high performance microprocessor chips, however, copper is now often used as an interconnect material. Copper is often preferred because of its low electrical resistivity, and its lower resistance-capacitance (RC) time delays in the metal interconnect that limit the performance of high-speed logic chips. Electrochemical deposition of copper is preferred because of its trench-filling capacity in the damascene process, and the relatively low cost of the damascene manufacturing process.
Copper damascene and copper dual damascene manufacturing is becoming more common due to the performance of copper interconnect material and the cost advantages of the dual damascene process. In the damascene process, a trench pattern is defined by etching through the dielectric materials. The trenches are then filled with electroplated copper and the interconnect pattern is obtained through a subsequent CMP (Chemical Mechanical Polishing) process. Copper damascene refers to the process where vertical copper interconnects (called plugs or vias) are formed between different layers of metal. Copper dual damascene refers to the process where the vertical plugs and the layers of metal are all formed in the same step. Copper dual damascene involves etching vias into the oxide, filling with copper, and then polishing down to the top of the copper to leave the horizontal copper layer and the vertical copper plugs. This type of manufacturing requires strict control of electroplating and polishing of the copper.
Electroplating is the preferred method for depositing the copper interconnect material to fill the trenches because of its trench filling capacity and its relatively low cost.
Copper electroplating from acidified copper sulfate is commonly used in the industry. Acidic copper plating solutions typically consist of three main components: (1) copper sulfate, which is the source of copper and is typically in the range of 0.2 to 1.0 M, (2) sulfuric acid, which provides conductivity to the electrolyte and is typically in the range of 0.5 to 1.1 M, and (3) various additives, which are typically present at 1 weight percent or below.
Recently, copper alkane sulfonate and perfluoroalkanesulfonate salts have shown an advantage in some aspects over the copper sulfate salts for the deposition of copper interconnects. See “Copper Sulfonate Electrolytes for Metallization of Interconnect Technology,” N. M. Martyak, R. Mikkola, American Electroplaters and Surface Finishing Conference, Chicago, Ill., Jun. 26, 2000. This reference discloses copper electrodeposition from methanesulfonate, ethanesulfonate, propanesulfonate, and trifluoromethanesulfonate solutions.
A low free acid concentration may be desirable because there is less likelihood of damage to the very thin copper seed layer. If the copper seed layer is damaged, it will lead to non-uniformity or void formation in the copper interconnects. But if free acid is present, a wider free acid range latitude makes it easier to control plating uniformity.
Plating solutions that produce less overfill are desirable. Less overfill is desirable because the copper coated substrates need to be planarized as part of the damascene or dual damascene process. With less overfill, there is less planarization required.
Plating efficiency can also be improved by improving conductivity of the solution.
Higher electrolyte conductivity requires less voltage to plate at a given current density, which in turn lowers energy consumption.
Thus, the need exists for an electrolytic solution having a low or no free acid concentration, having good conductivity, and having less overfill during copper plating. Additionally, the need exists for an electrolytic solution having a wide free acid range latitude, having good conductivity, and having less overfill during copper plating.
Alternatively, copper plating can be achieved by chemical methods, such as electroless plating. In electroless plating, reduction of dissolved copper ions to metallic copper is achieved by chemical means through the action of a reducing agent. Usually the chemical reduction of copper ion to metallic copper is catalyzed by a metallic seed layer, such as colloidal Pd. The performance of electroless plating solutions can be influenced by the structure of the counter anion. Thus, the need exists for counter anions for use in copper electroless plating solutions that improves the wetting and plating performance of these solutions.